actions-marketplace-validations/SystemVerilog Linter
SystemVerilog source code check by svlint
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Inputs
| name | description | required | default |
|---|---|---|---|
| files | Paths to SystemVerilog source files. | no | — |
| filelists | Paths to filelist files. | no | — |
| ruleset | Name of a ruleset, e.g "parseonly", "simsynth", etc. | no | — |
Outputs
no outputs