chipsalliance/verible-formatter
This action formats Verilog/SystemVerilog code
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- Scorecard Score
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- Maintenance Recency
- Stale
- License
- None
Inputs
| name | description | required | default |
|---|---|---|---|
| parameters | Additional parameters passed to formatter executable | no | "" |
| files | Optional array of files with source code to format | no | ./**/*.{v,sv} |
| github_token | GITHUB_TOKEN | — | "" |
| reviewdog_reporter | -reporter option to reviewdog | — | github-pr-review |
| fail_on_formatting_suggestions | If there are any formatting issues in the codebase, the action will return with an error | no | false |
| verible_version | Use selected Verible version (defaults to latest release) | — | latest |
Outputs
no outputs