jge162/Verilog Compiler
Quickly run your Verilog code and verify it is error-free
View on GitHubTrust Signals
- Scorecard Score
- not yet scored
- Maintenance Recency
- Stalelast commit Nov 2, 2024
- License
- GPL 3.0
- Runtime
- Deprecated runtime
Pinned Snippet
uses: jge162/verilog_compiler@5e8574b12e35d931a8ff195fe624772468052453 # 1.0.0tags can be moved; commit SHAs can't. why a SHA?
Inputs
| name | description | required | default |
|---|---|---|---|
| repo-token | Access token. | yes | — |
| configuration-path | Path to configuration file. | yes | — |
| sync-labels | Synchronize labels. | — | true |
| repository | Owner/repo name. | — | ${{ github.repository }} |
| ref | Checkout reference. | — | ${{ github.event.ref }} |
Outputs
no outputs